This application claims the priority benefit of Taiwan application serial No. 90122078, filed Sep. 6, 2001.
1. Field of Invention
The present invention relates to a structure of a semiconductor device and a method for manufacturing the semiconductor device. More particularly, the present invention relates to a structure of a MOSEFT and a method for manufacturing the MOSEFT.
2. Description of Related Art
With the gradually shrunk line width of the MOS, the leakage occurs easily at a portion of the source/drain far from the gate. The leakage can be decreased by forming a gate dielectric layer with a relatively thin thickness. However, when the line width is shrunk down below 0.1 micron, even the extremely thin gate dielectric layer cannot block the leakage. In order to solve the problem mentioned above, Professor Chenming Hu in UC Berkeley suggests two solutions. One is to use a substrate with a relatively thin thickness in the formation of the MOSFET. Therefore, there is no conductive path far from the gate. The other solution is to form a MOSFET with a double-gate structure surrounding the channel region so that the whole channel region is well controlled by the gate electric field. Hence, the on-current is increased and the leakage is decreased.
According to the concepts provided by professor Hu, a fin-type field effect transistor (FET) is developed. FIGS. 1A through 1C are schematics of the structure of a fin-type FET, wherein FIG. 1B is a cross-sectional view of a portion of FIG. 1A along line I-Ixe2x80x2 and FIG. 1C is a cross-sectional view of a portion of FIG. 1A along line II-IIxe2x80x2. The method for manufacturing the fin-type FET comprises the steps of providing a silicon-on-insulator (SOI) substrate 100. The thickness of the silicon layer (not shown) on the insulation layer 105 is 100 nm. Then, the thickness of the silicon layer is scaled down to 50 nm by performing the thermal oxidation. A hard mask layer 110 made of low temperature oxide (LTO) is formed on the silicon layer. A photolithography with a 100 keV electron beam and an anisotropic etching process are performed to pattern the hard mask layer 110 and the silicon layer to form a fin-type silicon layer 120 with a width about 20xcx9c50 nm. A poly Sixe2x80x94Ge layer (not shown) and a hard mask layer 130 made of LTO are subsequently formed over the substrate 100. The hard mask layer 130 and the poly Sixe2x80x94Ge layer are patterned to form a raised source 140 and a raised drain 150 with a thickness far larger than fin-type silicon layer 120.
As shown in FIG. 1A together with FIGS. 1B and 1C, a conformal silicon nitride layer (not shown) is formed over the substrate 100. An anisotropic etching process is performed to pattern the conformal silicon nitride layer into a spacer 160. In the anisotropic etching process, an over-etch step is performed even after a portion of the silicon nitride layer over the hard mask layer 130 is completely removed. Thus, a spacer formed on the side-wall of the fin-type silicon layer 120 with a relatively small thickness is totally removed but spacers 160 formed on the side-walls of the raised source 140 and the raised drain 150 still remains. As shown in FIGS. 1A and 1B, the side-wall of the fin-type silicon layer 120 is oxidized to form gate oxide layer 170. A poly Sixe2x80x94Ge layer (not shown) is formed over the substrate 100 to fill a space 190 between the spacers 160. Then, the poly Sixe2x80x94Ge layer is patterned to form a gate 180.
Since the electron beam photolithography is used in the method for manufacturing fin-type FET to define the fin-type silicon layer 120, the width of the fin-type silicon layer 120 can be scaled down to about 20xcx9c50 nm in order to prevent the device from leakage. Moreover, as shown in FIGS. 1A and 1C, because electric field induced by the gate 180 is passing through both side-walls of the fin-type silicon layer 120, the on-current of the device is relatively large. Nevertheless, because of the use of the SOI substrate, the cost of the device is high. Besides, during the formation of the spacer on the side-wall of the raised source and the raised drain, the side-wall of the fin-type silicon layer is damaged by the over-etch process so that the surface quality of the channel is poor and the performance of the device is worse. Additionally, it is hard to control the condition for forming the raised source and the raised drain to reduce source/drain resistance. Furthermore, since the width of the fin-type silicon layer 120 of the fin-type FET is relatively small in order to block the leakage, it is necessary to use the uncommon electron beam photolithography and the subsequent anisotropic etching process is hard to controlled and will damage the fin surface.
The invention provides a MOSFET structure with relatively less leakage phenomenon and relatively large on-current.
The invention also provide a method for manufacturing a MOSFET to decrease the leakage in the device and to increase the on-current of the device.
The MOSEFT provided by the invention comprises a substrate, an insulating layer, a spacer, a doped semiconductive layer, a gate dielectric layer, a gate and a source/drain region. The substrate possesses a trench formed therein. The insulating layer is located at the bottom of the trench. The spacer is located on the side-wall of the trench. The doped semiconductive layer spans the trench and partially covers the trench. The gate dielectric layer is located on the top surface and the bottom surface of the doped semiconductive layer. The gate is located on the gate dielectric layer, wherein the gate surrounds a portion of the doped semiconductive layer over the trench. The source/drain region is located in the substrate adjacent to the portion of the doped semiconductive layer surrounded by the gate.
The method for manufacturing a MOSFET provided by this invention comprises the steps of providing a substrate. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed, and a spacer is formed on the side-wall of the trench. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate. The doped semiconductive layer is patterned to form a device region, wherein the device region spans the sacrificial layer to expose a portion of the sacrificial layer. The sacrificial layer is removed. A gate dielectric layer is formed on the top surface and the bottom surface of the device region. A conductive layer is formed on the gate dielectric layer. The conductive layer is patterned to form a horizontal surround gate surrounding the channel region. A source/drain region is formed in a portion of the substrate adjacent to the channel region.
In the present invention, because the extra-thin doped semiconductive layer is used as a channel region, there is no channel portion far from the gate. Moreover, since the horizontal surround gate surrounds the channel region, the channel region is well controlled by the electric field. Therefore, the leakage can be greatly decreased and the on-current can be largely increased. Besides, the extra-thin doped semiconductive layer replaces the conventional SOI film to be a channel region, so that the wafer cost can be decreased. Furthermore, by comparing it with the fin-type FET, since the surface of the doped semiconductive layer in the present invention is not exposed by dry etching, the performance of the device won""t be affected. Also, the source/drain region is formed by the conventional doping process in the invention. It is not necessary to form the raised source/drain. Therefore, the manufacturing process can be well controlled. Further, the thickness of the channel region depends on the thickness of the doped semiconductive layer. Therefore, the issues caused by the electron beam lithography and the anisotropic etching process can be totally solved.
In addition, since there is a spacer between the gate and the source/drain region beside the side-wall of the trench, the parasitic capacitance between the gate and the source/drain region can be quite small. Similarly, since there is an insulating layer between the gate and the bottom of the trench, the parasitic capacitance between the gate and the substrate can be quite small.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.